1. Field of the Invention
The present invention relates to an integrated circuit in which a gate array and memory are combined on the same semiconductor substrate, more particularly to the metalized interconnection pattern of such an integrated circuit.
2. Background Information
Integrating a gate array with memory is a known technology. The memory, which may be a read-only memory (ROM), random-access memory (RAM), or other type of memory, is typically surrounded by a sea of gates, which is a type of channelless gate array. The gates can be interconnected according to the customer's specifications to provide specialized logic functions together with memory in a single device.
The gates are interconnected by patterning multiple metal layers to form interconnection lines. At least three layers of metal interconnecting lines are normally used for the gate interconnections. The first two of these layers are also normally used for interconnections within the memory part of the device.
In conventional devices of this type, the metal interconnecting lines in each layer are all routed in the same direction, typically at right angles to the interconnecting lines in the next layer, and the metal interconnecting lines of the gate array are routed so as not to pass over the memory area. One reason why gate-array interconnections are not routed over memory circuits is to avoid memory malfunctions that might be caused by crosstalk from gate-array signal lines. Another reason is to avoid having the operating speed of the memory reduced by the increased capacitance that memory signal lines would acquire if they were to be paralleled by overlying gate-array interconnecting lines.
However, the conventional practice greatly constrains the routing of interconnecting lines in the gate array since all gate interconnections must avoid the forbidden zone above the memory. One undesirable result is that the routing process becomes difficult, requiring extra time and resources (human resources and computer resources), hence increasing the cost of designing the device. Another undesirable result is that the percentage of gates that can be utilized is reduced. This may force the customer either to curtail the logic functions implemented in the device, or to select a larger and more expensive device with more gates.